1. Field of the Invention
The present invention relates generally to an electrostatic discharge input and power clamp circuit for high cutoff frequency technology radio frequency (RF) applications. More particularly, the subject invention relates to an electrostatic discharge input and power clamp circuit for high cutoff frequency technology RF applications with low voltage trigger elements and low power applications, and utilizing a forward biased junction trigger device and a low capacitance ESD NPN clamp transistor.
2. Discussion of the Prior Art
The present invention relates generally to electrostatic discharge circuits, and more specifically pertains to electrostatic discharge power clamp circuits for high frequency RF applications.
Electrostatic Discharge (ESD) events, which can occur both during and after manufacturing of an Integrated Circuit (IC), can cause substantial damage to the IC. ESD events have become particularly troublesome for CMOS and BiCMOS chips because of their low power requirements and extreme sensitivity.
A significant factor contributing to this sensitivity to ESD is that the transistors of the circuits are formed from small regions of N-type materials, P-type materials, and thin gate oxides. When a transistor is exposed to an ESD event, the charge applied may cause an extremely high current flow to occur within the device, which can, in turn cause permanent damage to the junctions, neighboring gate oxides, interconnects and/or other physical structures.
Because of this potential damage, on chip ESD protection circuits for CMOS and BiCMOS chips is essential. In general, such protection circuits require a high failure threshold, a small layout size and a low Resistive/Capacitive (RC) delay so as to allow high speed applications.
An ESD event within an IC can be caused by a static discharge occurring at one of the power lines or rails. In an effort to guard the circuit against damage from the static discharge, circuits referred to as ESD clamps are used. An effective ESD clamp will maintain the voltage at the power line to a value which is known to be safe for the operating circuits, and not interfere with the operating circuits under normal operating conditions.
An ESD clamp circuit is typically constructed between a positive power supply (e.g. VDD) and a ground plane, or a ground plane and a negative power supply (Vss). The main purpose of the ESD clamp is to reduce the impedance between the rails VDD and VSS so as to reduce the impedance between the input pad and the VSS rail (i.e. discharge of current between the input to VSS), and to protect the power rails themselves from ESD events.
The never ending demand by consumers for increased speed in Radio Frequency (RF) devices has resulted in some unique challenges for providing ESD protection in these high speed applications. More specifically, the physical size (e.g. breakdown voltage) and loading effects of the ESD devices must now be considered in such high speed applications (e.g. 1–200 GHz range). The capacitive loading of the ESD device itself becomes a major concern for chips running at high frequencies, since the capacitive loading has an adverse effect on performance. For example, the capacitive loading effect of a typical ESD input device at a frequency of 1 GHz is 0.5 pF, 10 GHz–0.1 pF, and at 100 GHz–0.05 pF, 200 GHz–0.01 pF.
For an input pad, having a low capacitance and low trigger voltage ESD network are keys to provide ESD solutions for high speed circuits. Hence an input ESD device must have the highest performance element with the lowest capacitance and the lowest trigger condition. RF technologies can have a plurality of transistor frequencies (e.g. typically one, two or three). Moreover a high frequency transistor typically has a lower capacitance compared to a high breakdown transistor.
For an ESD power clamp, it is important to provide a low voltage trigger condition to allow for a low voltage turn-on above the power supply voltage condition. For RF CMOS, Silicon Germanium (SiGe) and Silicon Germanium Carbon (SiGeC) technologies, the frequencies of the devices are increasing. Silicon Germanium technology current gain cutoff frequencies have increased to 120, 200 and 300 GHz. As the cutoff frequency increases, the architecture of the transistor is modified to address improved performance conditions. In each technology generation, the power supply voltage is reduced as well.
Additionally, on input pins, circuits with small signal swings well below the power supply can allow for ESD input networks whose maximum signal swing is well below the BVCEO (breakdown voltage from collector to emitter) of the high fT (unity current gain cutoff frequency) transistor supported in a Bipolar or BiCMOS technology. There are transistor logic standards, such as open drain configurations, Gunning transistor logic (GTL) and potentially other standards, where the maximum voltage observed in a CMOS circuit (or BiCMOS, or pure Bipolar) network is such that the signal swing is well below the BVCEO of at least one transistor in the technology. For low power applications, the voltage can be set to a level well below the BVCEO of a transistor. For a SiGe transistor, a 100 GHz transistor will have a BVCEO of approximately 2 Volts, and a 200 GHz transistor will have a BVCEO of approximately 1 Volt.
Additionally, the power supply of the semiconductor chip may be reduced in a mixed signal application. In this case, the power supply condition on CMOS circuits may be reduced. Additionally, the power supply condition on the product may be reduced for power saving, power management, and low power applications. To provide good ESD protection, it is then possible to provide an ESD input pad network or an ESD power clamp below the power supply conditions.
The prior art as developed to date has been constrained by the Johnson Limit as discussed below in providing a low trigger voltage condition for ESD protection circuits, particularly on-chip ESD protection circuits for CMOS and BiCMOS chips for RF applications.
It would, therefore, be a distinct advantage to have an ESD power clamp that could provide substantial benefits in high speed device technologies and provide a low trigger voltage condition for RF applications, mixed signal environments, and low power applications. The present invention provides such an ESD clamp.